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56f800 16-bit digital signal controllers freescale.com dsp56F802 rev. 9 01/2007 56F802 data sheet preliminary technical data

56F802 technical data, rev. 9 freescale semiconductor 3 56F802 block diagram jtag/ once port digital reg analog reg low voltage supervisor program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800 core pab pdb xdb2 cgdb xab1 xab2 interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset reset applica- tion-specific memory & peripherals interrupt controller program memory 8188 x 16 flash 1024 x 16 sram boot flash 2048x 16 flash data memory 2048 x 16 flash 1024 x 16 sram cop/ watchdog sci0 or gpio quad timer d or gpio quad timer c a/d1 a/d2 adc 2 2 3 2 6 pwm outputs pwma 16 16 vcapc v dd v ss *v dda v ssa 5 22 3 ? ? ? ? ? ? ? ? vref pll relaxation oscillator . * includes tcs pin which is reserv ed for factory use and is tied to vss fault a0 ? up to 30 mips operation at 60mhz core frequency ? up to 40 mips operation at 80mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ? hardware do and rep loops ? 6-channel pwm module with fault input ? two 12-bit adcs (1 x 2 channel, 1 x 3 channel) ? serial communicatio ns interface (sci) ? two general purpose quad timers with 2 external outputs ?8k 16-bit words (16kb) program flash ?1k 16-bit words (2kb) program ram ?2k 16-bit words (4kb) data flash ?1k 16-bit words (2kb) data ram ?2k 16-bit words (4kb) boot flash ? jtag/once tm port for debugging ? on-chip relaxation oscillator ? 4 shared gpio ? 32-pin lqfp package 56F802 general description
56F802 technical data, rev. 9 4 freescale semiconductor part 1 overview 1.1 56F802 features 1.1.1 processing core ? efficient 16-bit 56800 family controller engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80 mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators including extension bits ? 16-bit bidirectional barrel shifter ? parallel instruction set with un ique processor addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stac k with depth limited only by memory ? jtag/once debug programming interface 1.1.2 memory ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low-cost, high-volume flash solution ?8k 16 bit words of program flash ?1k 16-bit words of program ram ?2k 16-bit words of data flash ?1k 16-bit words of data ram ?2k 16-bit words of boot flash ? programmable boot flash supports customized boot co de and field upgrades of stored code through a variety of interfaces (jtag) 1.1.3 peripheral circuits for 56F802 ? pulse width modulator (pwm) with six pwm outp uts with deadtime insertion and fault protection; supports both center- and edge-aligned modes ? two 12-bit, analog-to-digital converters (adcs), 1 x 2 channel and 1 x 3 channel, which support two simultaneous conversions; adc and pwm modules can be synchronized ? two general purpose quad timers w ith two external pins (or two gpio) ? serial communication interface (sc i) with two pins (or two gpio) ? four multiplexed general purpose i/o (gpio) pins
56F802 description 56F802 technical data, rev. 9 freescale semiconductor 5 ? computer-operating properly (cop) watchdog timer ? external interrupts via gpio ? trimmable on-chip relaxation oscillator ? external reset pin for hardware reset ? jtag/on-chip emulation (once?) for unobtrusi ve, processor speed-ind ependent debugging ? software-programmable, phase locked loop-based frequency synthesizer for the controller core clock 1.1.4 energy information ? fabricated in high-density cmos with 5v-tolerant, ttl-compatible digital inputs ? uses a single 3.3v power supply ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available ? integrated power supervisor 1.2 56F802 description the 56F802 is a member of the 56800 core-based family of processors. it combines, on a single chip, the processing power of a dsp and the func tionality of a microcontro ller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost , configuration flexibility, and compact program code , the 56F802 is well-sui ted for many applications . the 56F802 includes many peripherals that are especi ally useful for applications such as motion control, home appliances, encoders, tachometers, limit switches, power supply and control, e ngine management, and industrial control for power, lighting, automation and hvac. the 56800 core is based on a harvard-style architectur e consisting of th ree execution uni ts operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor- style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instru ction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the 56F802 supports program executi on from either internal or extern al memories. two data operands can be accessed from the on-chip data ram per instruction cycle. th e 56F802 also provides and up to 4 general purpose input/output (gpio) line s, depending on peripheral configuration. the 56F802 controller includes 8k wo rds (16-bit) of program flash and 2k words of data flash (each programmable through the jtag port) with 1k words of both program and data ram. a total of 2k words of boot flash is in corporated for easy customer-inclusion of field-programmable software routines that can be used to program the ma in program and data flash memory ar eas. both program and data flash memories can be independently bulk er ased or erased in page sizes of 256 words. the boot flash memory can also be either bulk or page erased. a key application-specific feature of the 56F802 is the inclusion of a puls e width modulator (pwm) module. this modules incorporat es six complementary, individuall y programmable pwm signal outputs to enhance motor control functi onality. complementary operation permits programmable dead-time
56F802 technical data, rev. 9 6 freescale semiconductor insertion, and separate top and bot tom output polarity control. the up- counter value is programmable to support a continuously variable pwm frequency. both edge- and center -aligned synchron ous pulse width control (0% to 100% modulation) are supported. the devi ce is capable of controlling most motor types: acim (ac induction motors), both bdc and bldc (brush and brushl ess dc motors), srm and vrm (switched and variable reluctance motors), and stepper motors. the pwms incorporate fault protection with sufficient output drive capabi lity to directly drive standard opto-isolators. a ?smoke-inhibit?, write-once protection feature for key parameters is also include d. the pwm is double-buffered and includes interrupt control to permit integral reload rates to be pr ogrammable from 1 to 16. the pwm modules provide a reference output to sync hronize the analog-to-digital converters. the 56F802 incorporates two 12-bit analog-to-digital c onverters (adcs) with a to tal of five channels. a full set of standard programma ble peripherals is pr ovided that include a serial communications interface (sci), and two quad ti mers. any of these interfaces can be used as general-purpose input/outputs (gpio) if that function is not required. an on-chip relaxation oscillat or eliminates the need for an external crystal. 1.3 state of the art development environment ? processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software ap plication creation with an expert knowledge system. ? the code warrior integrated development environm ent is a sophisticated to ol for code navigation, compiling, and debugging. a complete set of eval uation modules (evms) and development system cards will support concurrent engineering. together, pe, code warrior and evms create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 product documentation the four documents listed in table 1-1 are required for a complete desc ription and proper design with the 56F802. documentation is available from local frees cale distributors, freescale semiconductor sales offices, freescale literature dist ribution centers, or online at www.freescale.com . table 1-1 56F802 chip documentation topic description order number 56800e family manual detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set 56800efm dsp56f801/803/805/807 user?s manual detailed description of memory, peripherals, and interfaces of the 56f801, 56F802, 56f803, 56f805, and 56f807 dsp56f801-7um 56F802 technical data sheet electrical and timing specific ations, pin descriptions, and package descriptions (this document) dsp56F802 56F802 errata details any chip issues that might be present 56F802e
data sheet conventions 56F802 technical data, rev. 9 freescale semiconductor 7 1.5 data sheet conventions this data sheet uses the following conventions: overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
56F802 technical data, rev. 9 8 freescale semiconductor part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56F802 are organized into functional groups, as shown in table 2-1 and as illustrated in figure 2-1 . in table 2-2 through table 2-10 , each table row describes the signal or signals present on a pin. table 2-1 functional gr oup pin allocations functional group number of pins detailed description power (v dd or v dda ) 3 table 2-2 ground (v ss, v ssa, tcs) 4 table 2-3 supply capacitors 2 table 2-4 program control 1 table 2-5 pulse width modulator (pwm) port and fault input 7 table 2-6 serial communications interface (sci) port 1 1. alternately, gpio pins 2 table 2-7 analog-to-digital converter (adc) port (including v ref) 6 table 2-8 quad timer module port 2 table 2-9 jtag/on-chip emulation (once) 5 table 2-10
introduction 56F802 technical data, rev. 9 freescale semiconductor 9 figure 2-1 56F802 signals identi fied by functional group 1 1. alternate pin functionality is shown in parenthesis. 56F802 power port ground port power port ground port sci0 port or gpio v dd v ss v dda v ssa vcapc tck tms tdi tdo t rst jtag/once ? port pwma0-5 fault a0 txd0 (gpiob0) rxd0 (gpiob1) ana2-4, ana6-7 vref td1-2 (gpioa1-2) reset quad timer d or gpio adca port other supply port 2 3* 1 1 2 1 1 1 1 1 program control 6 1 1 1 5 1 2 1 * includes tcs pin which is reserved for factory use and is tied to vss
56F802 technical data, rev. 9 10 freescale semiconductor 2.2 power and ground signals table 2-2 power inputs no. of pins signal name signal description 2 v dd power ?these pins provide power to the intern al structures of the chip, and should all be attached to v dd. 1 v dda analog power ?this pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3v supply. table 2-3 grounds no. of pins signal name signal description 2 v ss gnd ?these pins provide grounding for the internal structures of the chip, and should all be attached to v ss. 1 v ssa analog ground ?this pin supplies an analog ground. 1 tcs tcs ?this schmitt pin is reserved for factory use and must be tied to v ss for normal use. in block diagrams, this pin is considered an additional v ss. table 2-4 supply capacitors and vpp no. of pins signal name signal type state during reset signal description 2 vcapc supply supply vcapc ?connect each pin to a 2.2 f or greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). for more information, refer to section 5.2
interrupt and program control signals 56F802 technical data, rev. 9 freescale semiconductor 11 2.3 interrupt and program control signals 2.4 pulse width modulator (pwm) signals 2.5 serial communications interface (sci) signals table 2-5 program control signals no. of pins signal name signal type state during reset signal description 1 reset input (schmitt) input reset ?this input is a direct hardware reset on the processor. when reset is asserted low, the controller is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the extboot pin. the internal reset signal will be deasserted synchronous with t he internal clocks, after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the once/jta g module. in this case, assert reset , but do not assert trst . table 2-6 pulse width modu lator (pwma) signals no. of pins signal name signal type state during reset signal description 6 pwma0-5 output tri-stated pwma0-5 ? these are six pwma output pins. 1 faulta0 input (schmitt) input faulta0 ?this fault input is used for disabling selected pwma outputs in cases where fault conditions originate off-chip. table 2-7 serial communications interface (sci0) signals no. of pins signal name signal type state during reset signal description 1 txd0 gpiob0 output input/ou tput input input transmit data (txd0) ?sci0 transmit data output port b gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is sci output.
56F802 technical data, rev. 9 12 freescale semiconductor 2.6 analog-to-digital converter (adc) signals 2.7 quad timer module signals 1 rxd0 gpiob1 input input/ output input input receive data (rxd0) ?sci0 receive data input port b gpio ?this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is sci input. table 2-8 analog to digita l converter signals no. of pins signal name signal type state during reset signal description 3 ana2-4 input input ana2-4 ?analog inputs to adc, channel 1 2 ana6-7 input input ana6-7 ?analog inputs to adc, channel 2 1 vref input input vref ?analog reference voltage. must be set to v dda - 0.3v for optimal performance. table 2-9 quad time r module signals no. of pins signal name signal type state during reset signal description 2 td1-2 gpioa1-2 input/ output input/ output input input td1-2 ?timer d channel 1-2 port a gpio ?these pins are general purpose i/o (gpio) pins that can be individually programmed as input or output pins. after reset, the default state is the quad timer input. table 2-7 serial commun ications interface (sci 0) signals (continued) no. of pins signal name signal type state during reset signal description
jtag/once 56F802 technical data, rev. 9 freescale semiconductor 13 2.8 jtag/once part 3 specifications 3.1 general characteristics the 56F802 is fabricated in high-density cmos with 5-volt tolera nt ttl-compatible di gital inputs. the term ?5-volt tolerant? refe rs to the capability of an i/o pin, bu ilt on a 3.3v compatib le process technology, to withstand a voltage up to 5.5v without damaging the devi ce. many systems have a mixture of devices designed for 3.3v and 5v pow er supplies. in such systems, a bus may carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to rece ive a maximum voltage of 3.3v 10% during normal operation without causing damage ). this 5v-tolerant capability th erefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels wi thout being damaged. absolute maximum ratings given in table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. table 2-10 jtag/on-chip emul ation (once) signals no. of pins signal name signal type state during reset signal description 1 tck input (schmitt) input, pulled low internally test clock input ?this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/once port. the pin is connected internally to a pull-down resistor. 1 tms input (schmitt) input, pulled high internally test mode select input ?this input pin is used to sequence the jtag tap controller?s state machine. it is sample d on the rising edge of tck and has an on-chip pull-up resistor. note: always tie the tms pin to v dd through a 2.2k resistor. 1 tdi input (schmitt) input, pulled high internally test data input ?this input pin provides a serial input data stream to the jtag/once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdo output tri-stated test data output ?this tri-statable output pin provides a serial output data stream from the jtag/once port. it is driven in the shift-ir and shift-dr controller states, and chan ges on the falling edge of tck. 1 trst input (schmitt) input, pulled high internally test reset ?as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure comple te hardware reset, trst should be asserted at power-up and whenever reset is asserted. the only exception occurs in a debugging environment, since the once/jtag module is under the control of the debugger. in this ca se it is not necessary to assert trst when asserting reset . outside of a debugging environment reset should be permanently asserted by grounding the signal, thus disabling the once/jtag module on the device. note: for normal operation, connect trst directly to v ss . if the design is to be used in a debugging environment, trst may be tied to v ss through a 1k resistor.
56F802 technical data, rev. 9 14 freescale semiconductor the 56F802 dc and ac electrical sp ecifications are prelim inary and are from de sign simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published afte r complete characterization and device qualificati ons have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 3-1 absolute maximum ratings characteristic symbol min max unit supply voltage v dd v ss ? 0.3 v ss + 4.0 v all other input voltages, excluding analog inputs v in v ss ? 0.3 v ss + 5.5v v voltage difference v dd to v dda v dd - 0.3 0.3 v voltage difference v ss to v ssa v ss - 0.3 0.3 v analog inputs anax, v ref v in v ss ? 0.3 v dda + 0.3v v current drain per pin excluding v dd , v ss , & pwm ouputs i ? 10 ma table 3-2 recommended operating conditions characteristic symbol min typ max unit supply voltage, digital v dd 3.0 3.3 3.6 v supply voltage, analog v dda 3.0 3.3 3.6 v voltage difference v dd to v dda v dd -0.1 - 0.1 v voltage difference v ss to v ssa v ss -0.1 - 0.1 v
general characteristics 56F802 technical data, rev. 9 freescale semiconductor 15 notes: 1. theta-ja determined on 2s2p test boards is frequently lower than would be observed in an application. determined on 2s2p thermal test board. 2. junction to ambient therma l resistance, theta-ja ( r ja ) was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural convection. theta-ja was also simulated on a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number of planes) per jesd51-6 and jesd51-7. the correct name for theta-ja for forced convection or with the non-single layer boards is theta-jma. 3. junction to case thermal resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate techniqu e with the cold plate temperature used as the "case" temperature. the basic cold plate measurement technique is described by mil-std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance wh en the package is being used with a heat sink. 4. thermal characterization parameter, psi-jt ( jt ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in jesd51-2. jt is a useful value to use to estimate junction temperature in steady stat e customer environments. adc reference voltage 1 vref 2.7 ? v dda v ambient operating temperature t a ?40 ? 85 c 1. vref must be 0.3v below v dda . table 3-3 thermal characteristics 6 characteristic comments symbol value unit note s 32-pin lqfp junction to ambient natural convection r ja 50.2 c/w 2 junction to ambient (@1m/sec) r jma 47.1 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma (2s2p) 38.7 c/w 1,2 junction to ambient (@1m/sec) four layer board (2s2p) r jma 37.4 c/w 1,2 junction to case r jc 17.8 c/w 3 junction to center of case jt 3.07 c/w 4 i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd x v dd + p i/o ) w junction to center of case p dmax (tj - ta) /r ja w 7 table 3-2 recommended operating conditions characteristic symbol min typ max unit
56F802 technical data, rev. 9 16 freescale semiconductor 5. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temper ature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. see section 5.1 from more details on thermal design considerations. 7. tj = junction temperature ta = ambient temperature 3.2 dc electrical characteristics table 3-4 dc electrical characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc 2.25 ? 2.75 v input low voltage (xtal/extal) v ilc 0 ? 0.5 v input high voltage (schmitt trigger inputs) 1 v ihs 2.2 ? 5.5 v input low voltage (schmitt trigger inputs) 1 v ils -0.3 ? 0.8 v input high voltage (all other digital inputs) v ih 2.0 ? 5.5 v input low voltage (all other digital inputs) v il -0.3 ? 0.8 v input current high (pullup/pulldown resistors disabled, v in =v dd ) i ih -1 ? 1 a input current low (pullup/pulldown resistors disabled, v in =v ss ) i il -1 ? 1 a input current high (with pullup resistor, v in =v dd ) i ihpu -1 ? 1 a input current low (with pullup resistor, v in =v ss ) i ilpu -210 ? -50 a input current high (with pulldown resistor, v in =v dd ) i ihpd 20 ? 180 a input current low (wit h pulldown resistor, v in =v ss ) i ilpd -1 ? 1 a nominal pullup or pulldown resistor value r pu , r pd 30 k output tri-stat e current low i ozl -10 ? 10 a output tri-stat e current high i ozh -10 ? 10 a input current high (analog inputs, v in =v dda ) 2 i iha -15 ? 15 a input current low (analog inputs, v in =v ssa ) 2 i ila -15 ? 15 a output high voltage (at ioh) v oh v dd ? 0.7 ? ? v
dc electrical characteristics 56F802 technical data, rev. 9 freescale semiconductor 17 output low voltage (at iol) v ol ? ? 0.4 v output source current i oh 4 ? ? ma output sink current i ol 4 ? ? ma pwm pin output source current 3 i ohp 10 ? ? ma pwm pin output sink current 4 i olp 16 ? ? ma input capacitance c in ? 8 ? pf output capacitance c out ? 12 ? pf v dd supply current i ddt 5 run 6 (80mhz operation) ? 120 130 ma run 6 (60mhz operation) ? 102 111 ma wait 7 ? 96 102 ma stop ? 62 70 ma low voltage interrupt, external power supply 8 v eio 2.4 2.7 3.0 v low voltage interrupt, internal power supply 9 v eic 2.0 2.2 2.4 v power on reset 10 v por ? 1.7 2.0 v 1. schmitt trigger inputs are: faulta0, tcs, tck, tms, tdi, reset , and trst 2. analog inputs are: ana[0:7], xtal and extal. specification assumes adc is not sampling. 3. pwm pin output source current measured with 50% duty cycle. 4. pwm pin output sink current measured with 50% duty cycle. 5. i ddt = i dd + i dda (total supply current for v dd + v dda ) 6. run (operating) i dd measured using 8mhz clock source. all inputs 0.2v from rail; outputs unl oaded. all ports configured as inputs; measured with all modules enabled. 7. wait i dd measured using external s quare wave clock source (f osc = 8mhz) into xtal; all inputs 0.2v from rail; no dc loads; less than 50pf on all outputs. c l = 20pf on extal; all ports configured as input s; extal capacitance linearly affects wait i dd ; measured with pll enabled. 8. this low voltage interrupt monitors the v dda external power supply. v dda is generally connected to the same potential as v dd via separate traces. if v dda drops below v eio , an interrupt is generated. functionality of t he device is guaranteed under transient conditions when v dda > v eio (between the minimum specified v dd and the point when the v eio interrupt is generated). 9. this low voltage interrupt monitors the internally regulated core power supply. if the output from the internal voltage is re gulator drops below v eic , an interrupt is generated. since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0v). table 3-4 dc electrical characteristics (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit
56F802 technical data, rev. 9 18 freescale semiconductor figure 3-1 maximum run idd vs. fr equency (see note 6. in table 3-4 ) 3.3 ac electrical characteristics timing waveforms in section 3.3 are tested using the v il and v ih levels specified in the dc characteristics table. in figure 3-2 the levels of v ih and v il for an input signal are shown. figure 3-2 input signal measu rement references figure 3-3 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state 10. power ? on reset occurs whenever the internally regulated 2.5v digital supply drops below 1. 5v typical. while power is ramping up, this signal remains active for as long as the internal 2.5v is below 1.5v typical no matter how long the ramp up rate is. the i nternally regulated voltage is typically 100 mv less than v dd during ramp up until 2.5v is reached, at which time it self regulates. 0 40 80 120 160 10 20 30 40 50 60 70 80 freq. (mhz) idd (ma) idd digital idd analog idd total v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time
flash memory characteristics 56F802 technical data, rev. 9 freescale semiconductor 19 ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 3-3 signal states 3.4 flash memory characteristics table 3-5 flash memory truth table mode xe 1 1. x address enable, all rows are disabled when xe = 0 ye 2 2. y address enable, ymux is disabled when ye = 0 se 3 3. sense amplifier enable oe 4 4. output enable, tri-state flash data out bus when oe = 0 prog 5 5. defines program cycle erase 6 6. defines erase cycle mas1 7 7. defines mass erase cyc le, erase whole block nvstr 8 8. defines non-volatile store cycle standby l l l l l l l l read h h h h l l l l word program h h l l h l l h page erase h l l l l h l h mass erase h l l l l h h h table 3-6 ifren truth table mode ifren = 1 ifren = 0 read read information block read main memory block word program program information block program main memory block page erase erase information block erase main memory block mass erase erase both blocks erase main memory block data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
56F802 technical data, rev. 9 20 freescale semiconductor table 3-7 flash timing parameters operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit figure program time t prog* 20 ? ? us figure 3-4 erase time t erase* 20 ? ? ms figure 3-5 mass erase time t me* 100 ? ? ms figure 3-6 endurance 1 1. one cycle is equal to an erase program and read. e cyc 10,000 20,000 ? cycles data retention 1 d ret 10 30 ? years the following parameters should only be used in the manual word programming mode prog/erase to nvstr set up time t nvs* ? 5 ? us figure 3-4 , figure 3-5 , figure 3-6 nvstr hold time t nvh* ? 5 ? us figure 3-4 , figure 3-5 nvstr hold time (mass erase) t nvh1* ? 100 ? us figure 3-6 nvstr to program set up time t pgs* ? 10 ? us figure 3-4 recovery time t rcv* ? 1 ? us figure 3-4 , figure 3-5 , figure 3-6 cumulative program hv period 2 2. thv is the cumulative high voltage programming time to the same row before next erase. the same address cannot be programmed twice before next erase. t hv ? 3 ? ms figure 3-4 program hold time 3 3. parameters are guaranteed by design in smart pr ogramming mode and must be one cycle or greater. *the flash interface unit provides registers for the control of these parameters. t pgh ? ? ? figure 3-4 address/data set up time 3 t ads ? ? ? figure 3-4 address/data hold time 3 t adh ? ? ? figure 3-4
flash memory characteristics 56F802 technical data, rev. 9 freescale semiconductor 21 figure 3-4 flash program cycle figure 3-5 flash erase cycle xadr yadr ye din prog nvstr tnvs tpgs tadh tprog tads tpgh tnvh trcv thv ifren xe xadr ye=se=oe=mas1=0 erase nvstr tnvs tnvh trcv terase ifren xe
56F802 technical data, rev. 9 22 freescale semiconductor figure 3-6 flash mass erase cycle 3.5 clock operation the 56F802 device clock is derived fr om an on-chip relaxation oscillat or. the internal pll generates a master reference frequency th at determines the speed at which chip operations occur. the precs bit in the pllcr (phase-loc ked loop control register) word (bit 2) must be set to 0 for internal oscillator use. 3.5.1 use of on-chip re laxation oscillator the 56F802 internal relaxation oscillat or provides the chip clock without the need for an external crystal or ceramic resonator. the fr equency output of this internal oscillator can be corrected by adjusting the 8-bit iosctl (internal oscillator control) register. each bit added or deleted changes the output frequency of the oscillator allowing incremental adjustment until the de sired frequency is achi eved. figures 9 and 10 show the typical characteristics of the 56F802 relaxation oscillator with respect to temperature and trim value. during factory production test, an os cillator calibration procedure is executed which determines an optimum trim value for a given device (8mhz at 25 o c). this optimum trim value is then stored at address $103f in the data flash information block and r ecalled during a trim rout ine in the boot sequence (executed after power-up and reset) . this trim routine automatically sets the oscillator frequency by programming the iosctl register with the optimum trim value. xadr ye=se=oe=0 erase nvstr tnvs tnvh1 trcv tme mas1 ifren xe
clock operation 56F802 technical data, rev. 9 freescale semiconductor 23 due to the inherent frequency tolerances require d for sci communication, cha nging the factory-trimmed oscillator frequency is not recomm ended. if modification of the boot flash contents are required, code must be included which retrieve s the optimum trim value (from address $103f in the data flash information block) and writes it to the iosctl register . note that the ifren bit in the data flash control register must be set in order to r ead the data flash information block. figure 3-7 typical relaxation oscillat or frequency vs. temperature (trimmed to 8mhz @ 25 o c) table 3-8 relaxation oscillat or characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c characteristic symbol min typ max unit frequency accuracy 1 1. over full temperature range. f ? + 2 + 5 % frequency drift over temp f/ t ? + 0.1 ? %/ o c frequency drift over supply f/ v ? 0.1 ? %/v 8.2 8.0 8.3 8.4 7.9 8.1 7.8 75 55 -40 35 -25 15 -5 85 temperature ( o c) output frequency
56F802 technical data, rev. 9 24 freescale semiconductor figure 3-8 typical relaxation oscillator frequency vs. trim value @ 25 o c 3.5.2 phase locked loop timing table 3-9 pll timing characteristic symbol min typ max unit frequency for the pll 1 1. an externally supplied reference cl ock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8mhz input crystal. 2. zclk may not exceed 80mhz. for additional information on zclk and f out /2, please refer to the occs chapter in the user manual. zclk = f op 3. will not exceed 60mhz for the dsp56F802ta60 device. 4. this is the minimum time required after the pll setup is changed to ensure reliable operation. f osc 4 8 10 mhz pll output frequency 2 f out /2 40 ? 80 3 mhz pll stabilization time 4 0 o to +85 o c t plls ? 10 ? ms pll stabilization time 4 -40 o to 0 o c t plls ? 100 200 ms 0 10 2030405060708090a0b0c0d0e0f0 5 6 7 8 9 10 11
reset, stop, wait, mode select, and interrupt timing 56F802 technical data, rev. 9 freescale semiconductor 25 3.6 reset, stop, wait, mode select, and interrupt timing figure 3-9 external level-sen sitive interrupt timing table 3-10 reset, stop, wait, mode select, and interrupt timing 1, 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf 1. in the formulas, t = clock cycle. for an operating frequency of 80mhz, t = 12.5ns. characteristic symbol min max unit reset assertion to address, data and control signals high impedance t raz ? 21 ns minimum reset assertion duration 2 omr bit 6 = 0 omr bit 6 = 1 2. circuit stabilization delay is required during reset when using an external cloc k or crystal oscillator in two cases: ? after power-on reset ? when recovering from stop state 3. parameters listed are guaranteed by design. t ra 275,000t 128t ? ? ns ns reset de-assertion to first external address output t rda 33t 34t ns edge-sensitive interrupt request width t irw 1.5t ? ns general purpose i/o pin irqa b) general purpose i/o t ig
56F802 technical data, rev. 9 26 freescale semiconductor 3.7 quad timer timing figure 3-10 timer timing table 3-11 timer timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf 1. in the formulas listed, t = clock cycle. for 80mhz operation, t = 12.5 ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit timer input period p in 4t+6 ? ns timer input high/low period p inhl 2t+3 ? ns timer output period p out 2t ? ns timer output high/low period p outhl 1t ? ns timer inputs timer outputs p outhl p outhl p out p in p inhl p inhl
serial communication interface (sci) timing 56F802 technical data, rev. 9 freescale semiconductor 27 3.8 serial communicati on interface (sci) timing figure 3-11 rxd pulse width figure 3-12 txd pulse width table 3-12 sci timing 4 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50pf characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max *2.5)/(80) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns rxd sci receive data pin (input) rxd pw txd sci receive data pin (input) txd pw
56F802 technical data, rev. 9 28 freescale semiconductor 3.9 analog-to-digital c onverter (adc) characteristics table 3-13 adc ch aracteristics characteristic symbol min typ max unit adc input voltages v adcin 0 1 1. for optimum adc performance, keep the minimum v adcin value > 250mv. inputs less than 250mv volts may convert to a digital output code of 0 or cause erroneous conversions. ? v ref 2 2. v ref must be equal to or less than v dda - 0.3v and must be greater than 2.7v. v resolution r es 12 ? 12 bits integral non-linearity 3 3. measured in 10-90% range. inl ? +/- 4 +/- 5 lsb 4 4. lsb = least significant bit. differential non-linearity dnl ? +/- 0.9 +/- 1 lsb 3 monotonicity guaranteed adc internal clock 5 5. guaranteed by characterization. f adic 0.5 ? 5 mhz conversion range r ad v ssa ? v dda v power-up time t adpu ? 2.5 ? msec conversion time t adc ? 6 ? t aic cycles 6 6. t aic = 1/ f adic sample time t ads ? 1 ? t aic cycles 6 input capacitance c adi ? 5 ? pf 6 gain error (transfer gain) 5 e gain 1.00 1.10 1.15 ? offset voltage 5 v offset +10 +230 +325 mv total harmonic distortion 5 thd 55 60 ? db signal-to-noise plus distortion 5 sinad 54 56 ? ? effective number of bits 5 enob 8.5 9.5 ? bit spurious free dynamic range 5 sfdr 60 65 ? db spurious free dynamic range sfdr 65 70 ? db adc quiescent current (both adcs) i adc ? 50 ? ma v ref quiescent current (both adcs) i vref ? 12 16.5 ma
jtag timing 56F802 technical data, rev. 9 freescale semiconductor 29 1. parasitic capacitance due to package, pin to pi n, and pin to package base coupling. (1.8pf) 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing. (2.04pf) 3. equivalent resistance for the esd isolation resistor and the channel select mux. (500 ohms) 4. sampling capacitor at the sample and hold circuit. capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. (1pf) figure 3-13 equivalent anal og input circuit 3.10 jtag timing table 3-14 jtag timing 1, 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6 v, t a = ?40 to +85 c, c l 50 pf 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 80mhz operation, t = 12.5ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/8 the processor rate. 3. parameters listed are guaranteed by design. f op dc 10 mhz tck cycle time t cy 100 ? ns tck clock pulse width t pw 50 ? ns tms, tdi data setup time t ds 0.4 ? ns tms, tdi data hold time t dh 1.2 ? ns tck low to tdo data valid t dv ? 26.6 ns tck low to tdo tri-state t ts ? 23.5 ns trst assertion time t trst 50 ? ns 1 2 3 4 adc analog input
56F802 technical data, rev. 9 30 freescale semiconductor figure 3-14 test clock input timing diagram figure 3-15 test access port timing diagram figure 3-16 trst timing diagram tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t pw t cy input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t dv t ts t ds t dh trst (input) t trst
package and pin-out information 56F802 56F802 technical data, rev. 9 freescale semiconductor 31 part 4 packaging 4.1 package and pin-out information 56F802 this section contains package and pin-out informat ion for the 32-pin lqfp c onfiguration of the 56F802. figure 4-1 top view, 56F802 32-pin lqfp package pin 1 orientation mark pwma4 pwma5 td1 td2 txdo v ss v dd rxd0 tcs tck tms tdi vcapc2 tdo trst reset ana3 vref ana2 faulta0 v ss v dd v ssa v dda pwma3 pwma2 pwma1 vcapc1 pwma0 ana7 ana6 ana4 pin 25 pin 1 7 pin 9
56F802 technical data, rev. 9 32 freescale semiconductor table 4-1 56F802 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 pwma4 9 tcs 17 v dda 25 ana4 2 pwma5 10 tck 18 v ssa 26 ana6 3 td1 11 tms 19 v dd 27 ana7 4 td2 12 tdi 20 v ss 28 pwma0 5 txdo 13 vcapc2 21 faulta0 29 vcapc1 6 v ss 14 tdo 22 ana2 30 pwma1 7 v dd 15 trst 23 vref 31 pwma2 8 rxd0 16 reset 24 ana3 32 pwma3
package and pin-out information 56F802 56F802 technical data, rev. 9 freescale semiconductor 33 figure 4-2 32-pin lqfp mechanic al information (case 873a) please see www.freescale.com for the most current case outline. notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane a, b and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimensions b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more then 0.08 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protursion: 0.07 mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1 mm and 0.25 mm from the lead tip. dim a min max millimeters a1 a2 b b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 7.00 bsc e e e1 l1 1.00 ref o 07 o1 12 l 0.70 r1 0.08 0.20 r2 1.40 1.60 0.05 1.45 0.15 1.35 0.45 0.30 9.00 bsc s 0.20 ref 0.80 bsc 9.00 bsc 7.00 bsc 0.50 ref 0.08 --
56F802 technical data, rev. 9 34 freescale semiconductor part 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature c r ja = package junction-to-ambie nt thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a j unction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r ja = package junction-to-ambie nt thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and ca nnot be influenced by the user. the user controls the thermal environment to change the case-to-ambien t thermal resistance, r ca . for example, the user ca n change the air flow around the device, add a heat sink, change the mounting ar rangement on the printed ci rcuit board (pcb), or otherwise change the thermal diss ipation capability of the area su rrounding the device on the pcb. this model is most useful for ceramic pa ckages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for cera mic packages, in situations where the heat flow is split between a path to the case a nd an alternate path through the pcb, analysis of the device thermal performance may need the additional modeli ng capability of a sy stem level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperat ure of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactoril y answer whether the thermal performance is adequate, a sy stem level model may be appropriate. definitions: a complicating factor is the existe nce of three common definitions fo r determining the junction-to-case thermal resistance in plastic packages: ? measure the thermal resistance from the junction to th e outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. t j t a p d r ja () + = r ja r jc r ca + =
electrical design considerations 56F802 technical data, rev. 9 freescale semiconductor 35 ? measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junc tion to board thermal resistance. ? use the value obtained by the equation (t j ? t t )/p d where t t is the temperature of the package case determined by a thermocouple. the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top ce nter of the package case. the th ermocouple should be positioned so that the thermocouple junction re sts on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from th e junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a ther mocouple inserted at the interface between the case of the p ackage and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearan ce is important to mini mize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with th is technique, many engine ers measure the heat si nk temperature and then back-calculate the case temperatur e using a separate measurement of the thermal resistance of the interface. from this case temperat ure, the junction temperature is de termined from th e junction-to-case thermal resistance. 5.2 electrical design considerations use the following list of considerat ions to assure correct operation: ? provide a low-impedance path from the board power supply to each v dd pin on the controller, and from the board ground to each v ss (gnd) pin. ? the minimum bypass requirement is to place 0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configura tion is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacito rs tend to provide better performance tolerances. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56F802 technical data, rev. 9 36 freescale semiconductor ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead. ? bypass the v dd and v ss layers of the pcb with approximately 100 f, preferably with ceramic or tantalum capacitors which tend to provide better performance tolerances. ? because the controller?s output signals have fast rise and fall times, pcb trace le ngths should be minimal. ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in system s with higher capacitive loads that co uld create higher transient currents in the v dd and gnd circuits. ? take special care to minimize noise levels on the vref, v dda and v ssa pins. ? designs that utilize the trst pin for jtag port or once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . trst must be asserted at power up for proper operation. designs that do not requir e debugging functionality, su ch as consumer products, trst should be tied low. ? because the flash memory is programmed through the jtag/once port, designers should provide an interface to this port to allo w in-circuit flash programming.
electrical design considerations 56F802 technical data, rev. 9 freescale semiconductor 37 part 6 ordering information table 6-1 lists the pertinent information needed to pl ace an order. consult a freescale semiconductor sales office or authorized di stributor to determine availability and to order parts. *this package is rohs compliant. table 6-1 56F802 ordering information part supply voltage package type pin count ambient frequency (mhz) order number 56F802 3.0?3.6 v low profile plastic qu ad flat pack (lqfp) 32 80 dsp56F802ta80 56F802 3.0?3.6 v low profile plastic qu ad flat pack (lqfp) 32 60 dsp56F802ta60 56F802 3.0?3.6 v low profile plastic qu ad flat pack (lqfp) 32 80 dsp56F802ta80e* 56F802 3.0?3.6 v low profile plastic qu ad flat pack (lqfp) 32 60 dsp56F802ta60e*
56F802 technical data, rev. 9 38 freescale semiconductor
electrical design considerations 56F802 technical data, rev. 9 freescale semiconductor 39
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